(Not Applicable)
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package including a flex circuit which allows multiple chip packages to be quickly, easily and inexpensively assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant""s U.S. Pat. Nos. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages including flex circuits. The inclusion of the flex circuits in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significant increases in the production rate and resultant reductions in cost attributable to the reduced complexity of the assembly process.
In accordance with a first embodiment of the present invention, there is provided a stackable integrated circuit chip package which comprises a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the flex circuit is a conductive pattern. In addition to the flex circuit, the chip package comprises a frame which is attached to the substrate of the flex circuit. Also included in the chip package is an integrated circuit chip which is at least partially circumvented by the frame and electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit ship package.
In the first embodiment, the frame preferably has a generally rectangular configuration defining opposed pairs of longitudinal and lateral sides. The frame also defines a central opening for receiving the integrated circuit chip, with the top and bottom surfaces of the frame being attached to the top surface of the substrate. The substrate is preferably wrapped about the frame such that the first portion of the conductive pattern extends over a portion of the bottom surface of the frame, with the second portion of the conductive pattern extending over a portion of the top surface of the frame. More particularly, the substrate is wrapped about the longitudinal sides of the frame such that the first and second portions of the conductive pattern extend in spaced, generally parallel relation to each other over respective portions of the bottom and top surfaces of the frame.
The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof, with the substrate preferably being wrapped about the longitudinal sides of the frame such that the longitudinal peripheral edge segments of the substrate extend along respective ones of the longitudinal sides of the frame. The substrate is also sized relative to the frame such that the lateral sides of the frame protrude from respective ones of the lateral peripheral edge segments of the substrate, with the longitudinal peripheral edge segments of the substrate also extending to the central opening of the frame. In the chip package of the first embodiment, a pair of heat sinks may be attached to one or both of the lateral sides of the frame which extend beyond the lateral peripheral edge segments of the substrate.
The conductive pattern of the chip package of the first embodiment preferably comprises a first set of pads which are disposed on the bottom surface of the substrate, and a second set of pads which are disposed on the top surface of the substrate and electrically connected to respective ones of the pads of the first set. The integrated circuit chip is itself electrically connected to the pads of the second set. A plurality of copper bumps or solder bumps may be formed on respective ones of the pads of the first set for facilitating the electrical connection of the chip package to a mother board. The pads of the second set are preferably arranged in an identical pattern to those of the first set such that the pads of the second set are aligned with and electrically connected to respective ones of the pads of the first set. The electrical connection of the pads of the first and second sets to each other is preferably accomplished through the use of vias which are formed in the substrate and extend between respective aligned pairs of the pads of the first and second sets.
The integrated circuit chip of the chip package of the first embodiment preferably comprises a body having opposed, generally planar top and bottom surfaces. In addition to the body, the integrated circuit chip includes a plurality of conductive contacts which are disposed on the bottom surface of the body. The conductive contacts of the integrated circuit chip are electrically connected to respective ones of the pads of the second set. The conductive contacts are preferably arranged on the bottom surface of the body in an identical pattern to the pads of the second set, and are preferably electrically connected to respective ones of the pads of the second set via solder. The integrated circuit chip is preferably selected from the group consisting of a flip chip device and a fine pitch BGA device.
In the chip package of the first embodiment, a layer of epoxy is preferably disposed between the bottom surface of the body and the top surface of the substrate. Additionally, the substrate is preferably attached to the frame through the use of an acrylic film adhesive. The substrate is preferably fabricated from a polyamide having a thickness in the range of from about 1 mil to about 8 mils, with the frame preferably being fabricated from either a plastic material filled with a thermal enhancing material or a metal material. The chip package may be combined with a second chip package stacked upon the chip package, with the first portion of the conductive pattern of the second chip package being electrically connected to the second portion of the conductive pattern of the chip package. The electrical connection of the chip packages to each other is preferably accomplished through the use of a Z-axis film material or adhesive.
In accordance with a second embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising a flex circuit. In the second embodiment, the flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern which is disposed on the flex circuit. The chip package of the second embodiment also includes an integrated circuit chip which is electrically connected to the conductive pattern. The substrate of the chip package of the second embodiment is wrapped about and attached to at least a portion of the integrated circuit chip such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package. In the chip package of the second embodiment, the conductive pattern comprises the first and second sets of pads as described in relation to the chip package of the first embodiment. The electrical connection of the integrated circuit chip to the conductive pattern is accomplished in the chip package of the second embodiment in the same manner previously described in relation to the chip package of the first embodiment.
In the chip package of the second embodiment, the body of the integrated circuit chip preferably has a generally rectangular configuration defining a pair of longitudinal sides and a pair of lateral sides. The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof. The substrate is wrapped about the longitudinal sides of the body, such that the longitudinal peripheral edge segments of the substrate extend along the top surface of the body in spaced, generally parallel relation to each other. The first and second portions of the conductive pattern also extend in spaced, generally parallel relation to each other over respective portions of the bottom and top surfaces of the body of the integrated circuit chip. The substrate is preferably attached to the integrated circuit chip through the use of an acrylic film adhesive. Additionally, a layer of epoxy is preferably disposed between the bottom surface of the body and top surface of the substrate. The substrate of the chip package of the second embodiment is preferably fabricated from the same material having the same thickness range as previously described in relation to the chip package of the first embodiment.
In accordance with a third embodiment of the present invention, there is provided a stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern which is disposed thereon. The chip package of the third embodiment further comprises an integrated circuit chip which is electrically connected to the conductive pattern. The substrate is folded and attached to itself such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package. In the chip package of the third embodiment, the conductive pattern comprises the first and second sets of pads as described in relation to the chip package of the first embodiment. Additionally, the electrical connection of the integrated circuit chip to the conductive pattern is preferably accomplished in the same manner as previously described in relation to the chip package of the first embodiment.
In the chip package of the third embodiment, the body of the integrated circuit chip preferably has a generally rectangular configuration defining a pair of longitudinal sides and a pair of lateral sides. The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof. The substrate is folded such that the longitudinal peripheral edge segments thereof extend along and in substantially parallel relation to respective ones of the longitudinal sides of the body, with the first and second portions of the conductive pattern extending in generally parallel relation to each other. As will be recognized, the total thickness of the substrate at those regions whereat it is folded over itself is preferably such that the second portion of the conductive pattern is substantially flush with or extends along a plane disposed above the top surface of the body of the integrated circuit chip, thus allowing for the electrical connection of the second portion of the conductive pattern of the chip package to another stackable integrated circuit chip package. In the chip package of the third embodiment, the substrate is preferably attached to itself through the use of an acrylic film adhesive, with the chip package further preferably comprising a layer of epoxy disposed between the bottom surface of the body and the top surface of the substrate. The substrate in the chip package of the third embodiment is also preferably fabricated from the same material in the same thickness range as previously described in relation to the chip package of the first embodiment.
Further in accordance with the present invention, there is provided a method of assembling a stackable integrated circuit chip package constructed in accordance with the first embodiment of the present invention. The method comprises the initial step of electrically connecting an integrated circuit chip to a conductive pattern on a flexible substrate of a flex circuit. This particular step is itself preferably accomplished by first applying a layer of flux to the conductive contacts of the integrated circuit chip, and thereafter positioning the integrated circuit chip upon the substrate such that at least some of conductive contacts abut the conductive pattern. Thereafter, heat is applied to the integrated circuit chip and the substrate to facilitate the reflow of the solder disposed on the conductive contacts and electrical connection thereof to the conductive pattern.
In the preferred method, the above described initial heat application step is followed by the dispensation of a quantity of an epoxy onto the substrate along a side of the integrated circuit chip to facilitate the wicking of the epoxy between the integrated circuit chip and the substrate. At this time, the substrate preferably resides on a heated stage at a temperature of about 90 degrees Celsius. After the epoxy has been applied to the substrate, the heat applied to the integrated circuit chip and the substrate by the heated stage is then increased to a temperature of about 160 degrees Celsius for a time period of about 5 minutes to facilitate the hardening of the epoxy. The epoxy dispensation and subsequent heating step are preferably completed while a vacuum is being applied to the substrate to maintain the substrate in a generally flat orientation. Thereafter, the integrity of electrical connection of the conductive contacts of the integrated circuit chip to the conductive pattern is tested.
Upon the completion of the electrical connection of the integrated circuit chip to the conductive pattern, a frame is attached to the flex circuit such that the frame at least partially circumvents the integrated circuit chip. The attachment of the frame to the flex circuit is preferably accomplished by initially bonding two strips of an adhesive to the substrate along opposite sides of the integrated circuit chip. Thereafter, a pair of flex windows are punched through the substrate and respective ones of the adhesive strips, with the frame thereafter being attached to the adhesive strips. The bonding of the adhesive strips to the substrate is preferably completed by heating the adhesive strips and the substrate to a temperature of about 140 degrees Celsius and applying pressure to the adhesive strips for a time period of from about 5 seconds to about 10 seconds. To facilitate the attachment of the frame to the adhesive strips, the frame, adhesive strips, and substrate are preferably heated to a temperature of about 130 degrees Celsius, with pressure of about 20 psi being applied to the frame for a time period of about 5 seconds.
Following the attachment of the frame to the flex circuit, the flex circuit is wrapped about and secured to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to at least one other stackable integrated circuit chip package. To facilitate such wrapping, the substrate is preferably positioned upon a spaced pair of reciprocally movable wrapping fingers, with pressure then being applied to one side of the frame of the integrated circuit chip to force the frame and the integrated circuit chip between the wrapping fingers and facilitate the folding of the substrate upwardly along each of the opposed sides of the frame. The wrapping fingers are then moved toward each other to facilitate the wrapping of the substrate about the opposed sides of the frame. Heat is applied to the chip package at a temperature about 180 degrees Celsius for a time period of about 5 minutes after the movement of the wrapping fingers toward each other. This 5 minute time period is used to facilitate the curing of the adhesive, with the wrapping fingers being moved away from each other upon the elapse thereof to allow for the removal of the chip package from therebetween.
The present method may further comprise the additional step of electrically connecting the second portion of the conductive pattern of the chip package to the first portion of the conductive pattern of another stackable integrated circuit chip package to form a chip stack. Such electrical connection between the chip packages is preferably accomplished by first placing a Z-axis film between the first and second portions of the conductive patterns of the chip packages, and thereafter applying heat and pressure to the chip packages for a time period of about 1 minute to cure the Z-axis film. A plurality of copper bumps or solder bumps may then be formed on the first portion of the conductive pattern of the lowermost chip package of the chip stack, with the integrity of the electrical connection of the chip packages to each other than being tested.
Further in accordance with the present invention, there is provided methods for assembling chip packages constructed in accordance with the second and third embodiments as described above. These assembly methods are substantially similar to assembly method previously described in relation to the chip package of the first embodiment. More particularly, the assembly method related to the chip package of the second embodiment differs only in that the substrate is wrapped about opposed sides of the integrated circuit chip and adhered directly thereto due to the absence of the frame in the chip package of the second embodiment. In the assembly method related to the third embodiment, the substrate is folded over and adhered to itself.